1. Field of the Invention
The present invention generally relates to solving the problem of updating output driver impedances in a way that is transparent to the user.
2. Description of the Related Art
High performance memories require reliable and well-behaved output driver impedances, and also require transparent impedance updates. As system temperature and voltages drift, periodic impedance updates occur to maintain a near-constant output driver impedance. However, the impedance updates must occur in a manner that does not disrupt bus operation. For example, a binarily-controlled output driver changing from an impedance value of “011111” to “100000” will see a discontinuity in impedance as all bits change. Referring to the previous example, the target impedance of 50-Ohms may see an actual transition from 49-Ohms (“011111”) to 120-Ohms (“000000”) before returning to the ultimate value of 50-Ohms (“100000”). The impedance discontinuity is very undesirable and causes bus glitches and ultimately timing violations at the receiving device.
Another problem with conventional structures occurs in power-up cycles during initialization and periodicity of updates. Shifts in temperatures normally occur in periods that do not require very frequent updates. However, it is desired to have the optimum impedance after initialization cycles are completed. An impedance system employing Z binary bits require 2Z impedance updates. If impedance updates occur every Y cycles, then the number of power-up cycles is Y×2Z. If Z=7 and Y=256, then the number of power-up cycles becomes 32 K, exceeding the application requirements of 1 K.
The invention described below provides a structure and method that eliminates impedance discontinuity and improves startup performance.